HERE is a brief generic, typical timing diagram for a generic integrated circuit in a typical computer.





CMOS input signals, input enable delays, set-up and hold times, and address-to-output delay times are shown. The timing diagram assumes a positive-edge triggered device. These time parameters are typically measured in nanoseconds (billionths of a second), or picoseconds (trillionths of a second).

Vaughn's Summaries

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Timing Diagram

30

540-860

30

260

CMOS Input Signals

tF = Fall time (3ns max.)

tR = Rise time (3ns max.)

VIN = 0 to 3.0 Volts

VTH = 1.5 Volts

Set-up & Hold Times

tAH = Address Hold time (min.)

tAS = Address Set-up time (min.)


tDH = Data Hold time (min.)

tDS = Data Set-up time (min.)

Output Enable Times (max.)

tZH = OE-to-Output HIGH time

tZL = OE-to Output LOW time

Output Disable times (max.)

tHZ = Active HIGH-to-Hi-Z time

tLZ = Active LOW-to-Hi-Z time

Clock Timing

tCP = Clock Period (min.)

tCL = Clock Low time (min.)

tPW = Clock High time (min.)

Input Enable Delays

tCD = Clock Disable delay time (max.)

tCE = Clock Enable delay time (min.)

Output Delays (max.)

tAA = Address Access time

tPD0 = Clock-to-Output LOW time

tPD1 = Clock-to-Output HIGH time

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