Timing Diagrams

Vaughn's Summaries logo

Computer Summaries

Generic IC Timing Diagram

HERE is a brief generic, typical timing diagram for a generic integrated circuit in a typical computer.


CMOS input signals, input enable delays, set-up and hold times, and address-to-output delay times are shown. The timing diagram assumes a positive-edge triggered device. These time parameters are typically measured in nanoseconds (billionths of a second), or picoseconds (trillionths of a second).


Primary AC Timing Parameters of A Typical Integrated Circuit

CMOS Input Signals

tF = Fall time (3ns max.)

tR = Rise time (3ns max.)

VIN = 0 to 3.0 Volts

VTH = 1.5 Volts

Set-up & Hold Times

tAH = Address Hold time (min.)

tAS = Address Set-up time (min.)


tDH = Data Hold time (min.)

tDS = Data Set-up time (min.)

Output Enable Times (max.)

tZH = OE-to-Output HIGH time

tZL = OE-to Output LOW time

Output Disable times (max.)

tHZ = Active HIGH-to-Hi-Z time

tLZ = Active LOW-to-Hi-Z time

Clock Timing

tCP = Clock Period (min.)

tCL = Clock Low time (min.)

tPW = Clock High time (min.)

Input Enable Delays

tCD = Clock Disable delay time (max.)

tCE = Clock Enable delay time (min.)

Output Delays (max.)

tAA = Address Access time

tPD0 = Clock-to-Output LOW time

tPD1 = Clock-to-Output HIGH time



  Computer Summaries

  Adobe FrameMaker Cheat Sheet

Disk Drive Reliability

Powers of 2 Chart

  Apple Airport Configuration Diagram

Electronics Distributors, San Jose

Processor Evolution History

  Apple iMac Model Summary

Modem Block Diagram

Semiconductor Manufacturers

  Apple PowerMac G4 Summary

Networking Standards

Timing Diagram - Generic IC

  ASIC vs. FPGA Logic

PC Block Diagram

Video Resolution Chart

topofpage



Vaughn's Summaries (One-Pagers)
©2003, 2004 Vaughn Aubuchon ... All Rights Reserved
http://www.vaughns-1-pagers.com


This Vaughns Summaries Generic IC Timing Diagram web page was updated on 2007-05-10.